SanDisk and Toshiba announce 19nm NAND flash memory

Just last week IM Flash Technologies -- a joint venture between Intel and Micron Technology -- announced a new 20nm NAND memory chip manufacturing process touted as the smallest most advanced yet. But as it is common in the tech industry these titles never last too long. Case in point: Toshiba and SanDisk have announced plans to begin sampling NAND flash memory chips manufactured using a 19nm process technology before the end of this month.

The first product to be made on the 19nm process will be a 64Gbit (8GB) multi-level cell (2-bits-per-cell) flash memory chip, with high-volume production planned for the second half of 2011. At that time, SanDisk will also add 3-bits-per-cell products fabricated with the 19nm process technology to its lineup, according to the press release.

"We are excited to introduce the world's smallest and lowest-cost NAND flash chips based on industry-leading 19nm process technology in our ongoing collaboration with our manufacturing partner Toshiba," said Yoram Cedar, executive vice president and chief technology officer, SanDisk. "Products based on this technology are designed to enable new applications, form factors and consumer experience that will continue to drive the flash industry to new heights."

The companies said the smaller process would allow device makers to squeeze more storage in less space. There's no mention of the chip's actual dimensions besides citing the prospect of stacking a batch of 16 to deliver 128GB modules for use in mobile phones, tablet computers and other devices. The 19nm NAND chips are equipped with Toggle DDR2.0 to enhance data transfer speed, and use an All-Bit-Line architecture with proprietary programming algorithms and multi-level data storage management that will allegedly uphold performance and reliability.

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Micron develops 'Hyper Memory Cube' technology

Memory-chip maker Micron has unveiled a new hybrid memory technology that it claims should offer a 20-fold performance boost over chips currently used in personal computers, while reducing the size of the chip and consuming about one-tenth of the power. Speaking to Cnet, the company said its development breaks a longstanding problem referred to as the "memory wall" to deliver "a staggering amount of DRAM bandwidth directly to the processor."

Essentially, DRAM performance today is constrained by the capacity of the data channel that sits between the memory and the processor. This channel often becomes a choke point for data, no matter how much faster the DRAM chip itself gets, which was more recently evidenced in the industry's slow transition from DDR2 to DDR3 as desktop and notebook makers weren't really seeing a big enough improvement to warrant the move.

There isn't much in the way of technical details at the moment but it would appear that Micron is leveraging memory architecture knowledge from its Numonix acquisition last year to stack several memory layers atop each other and adding a controller chip right into the memory substrate. This not only allows a higher speed bus that will go from the controller chip to the CPU, it also means that memory could be packed more densely in a given volume.

The company hopes to see the so-called "Hybrid Memory Cube" technology in server and networking markets as early as 2012, with significant volumes in 2013, and could then start to work their way toward the consumer space in 2015.

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